Modelsim has a pretty clumsy and ugly user interface(atleast in linux). Moreover, command line gives more control and makes automation easier. Lets see how we can simulate VHDL project using modelsim command line tools. Before starting, make sure you have modelsim’s bin directory in your PATH. To demonstrate, I will reuse the fileio example. Lets assume you have the above vhdl files in a project directory. In the command line, change to the project directory.
First we have to create a work library:
Now, compile the VHDL files:
vcom fileio.vhd gen.vhd
Note: The files should be listed in hierarchical order.
To simulate using GUI:
Note: vsim takes the name of the top level module to be simulated, not the name of the top level module’s VHDL file.
Adding the -c option starts the simulator in command line interactive mode.
vsim -c fileio
You should be in VSIM’s prompt. From here you can type commands to add signal to the wave, run simulation, write to vcd file, etc.
Show available signals
The VSIM command to list all available signals
You can also list all available signals in an instance
To unambiguously show signals of an instances down the hierarchy
Adding signals to wave
add wave i_a
You can also add signals of an instance down the hierarchy
add wave /fileio/gen_inst/a_i
Run the simulation
To run the complete simulation
To run for a specified time
Follow this blog post to generate VCD waveform from command line.
The best thing is you don’t have to type these commands every time you launch vsim. You can automate the process by specifying the .do in the vsim command. The .do should contain the list of commands you want to execute to run the simulation.
Here is the updated command to lauch fileio example:
vsim -c -do fileio.do fileio