VHDL: File i/o as testbench stimulus

It is not always practical to hard code the test bench stimulus in VHDL code. This article introduces a way to read the stimulus stored in a text file and feed the DUT.

First, lets look at the DUT. It is a simple 4 bit adder.

Now lets create the test bench for gen.

The process input_gen reads the input from the input file “in.txt” and the process output_gen writes the output to output file “out.txt”.

The file variable inp_file opens the file “in.txt” in read mode and the file variable out_file opens the file “out.txt” in write mode. Both “in.txt” and “out.txt” are stored as text file.

Each line in “in.txt” has one stimulus for all signals as integers. In this example, we have only two signals i_a and i_b. This is the syntax of one line in “in.txt”:

{{i_a stimulus}} {{i_bstimulus}}

Here is an example “in.txt”:

One line is read from “in.txt” every clock cycle using readline function into inline variable. The stimulus for each variable are read serially from inline using read function.