SystemVerilog interfaces gives us a very good tool to make the code cleaner and less error prone. If you have a group of ports that go together, you can group them into a single interface and reduce huge amount of code.
Thats great. But if you have a pure verilog module and want it to stay that way. How should we connect the interface to the pure Verilog module? Its easy as well. Just create an instance of a module and an instance of the interface. When you instantiate the verilog module use the interface’s members as module’s ports. Now you can drive your module through the interface or connect the module to another SystemVerilog module that accepts the same interface.