Crack and install Modelsim on linux

Note: Piracy is crime. Please don’t use or encourage pirated software. If you would like to evaluate Modelsim, try the evaluation version. If you still haven’t changed your mind, read on :P.

1) Install the required dependencies

2) Download modelsim 10.1c for linux and its corresponding crack.

3) Mount the downloaded modelsim iso and install modelsim.

mkdir /tmp/modelsim/
mount -o loop path-to-iso /tmp/modelsim
cd /tmp/modelsim
./install.linux

Note:Install modelsim under ~/modelsim/ directory. If you choose another location, please make sure you exchange the default location with your preferred location in the steps below.

4) Execute this script to crack modelsim

Comment the first two lines in the generated license.dat

#SERVER xxxx xxxxxxxxxxxx 27001
#VENDOR mgcld D:FEATURE mgc_s mgcld 2020.00 1-jan-2021 999 0 TS_OK

5) Fix libfreetype problem (Only required if you face this problem)
Try to start vsim

cd ~/modelsim/modeltech/linux_x86_64/
./vsim

If vsim reports the following error, your distro’s freetype library doesn’t play well with modelsim.

** Fatal: Read failure in vlm process (0,0)
Segmentation fault (core dumped)

Use the following script to compile custom freetype

6) Modelsim is ready to use! One last step, add these commands to ~/.bashrc to avoid executing every time you start a new terminal

Linux and Modelsim!!!! Ain’t it fun?

VHDL: std_logic/std_ulogic comparision

VHDL has a lot of things that don’t work as you expect it to work. One of those things are comparison operators.

Comparison of scalar std_ulogic family signals

Comparison of scalar built-in types like std_logic and std_ulogic work as expected.

Comparison of std_ulogic_vector

This is where the shit hits the fan. Your natural intuition would be to try something like this:

This won’t work because VHDL is a strongly types language. You cannot compare between std_ulogic_vector and integer types directly. If you want to compare an integer with a std_ulogic_vector, you have to either convert the integer to std_ulogic_vector or convert std_ulogic_vector to integer before comparing.

Another thing you can do to make this work is to express both of them in std_ulogic_vector.

Modelsim: compile and simulate VHDL from command line

Modelsim has a pretty clumsy and ugly user interface(atleast in linux). Moreover, command line gives more control and makes automation easier. Lets see how we can simulate VHDL project using modelsim command line tools. Before starting, make sure you have modelsim’s bin directory in your PATH. To demonstrate, I will reuse the fileio example. Lets assume you have the above vhdl files in a project directory. In the command line, change to the project directory.

First we have to create a work library:

vlib work

Now, compile the VHDL files:

vcom fileio.vhd gen.vhd

Note: The files should be listed in hierarchical order.

To simulate using GUI:

vsim fileio

Note: vsim takes the name of the top level module to be simulated, not the name of the top level module’s VHDL file.

Adding the -c option starts the simulator in command line interactive mode.

vsim -c fileio

You should be in VSIM’s prompt. From here you can type commands to add signal to the wave, run simulation, write to vcd file, etc.

Show available signals

The VSIM command to list all available signals

show -all

You can also list all available signals in an instance

show fileio
show gen_inst

To unambiguously show signals of an instances down the hierarchy

show /fileio/gen_inst

Adding signals to wave

add wave i_a

You can also add signals of an instance down the hierarchy

add wave /fileio/gen_inst/a_i

Run the simulation

To run the complete simulation

run -all

To run for a specified time

run <time>
run 100ps

Follow this blog post to generate VCD waveform from command line.

Automate simulation

The best thing is you don’t have to type these commands every time you launch vsim. You can automate the process by specifying the .do in the vsim command. The .do should contain the list of commands you want to execute to run the simulation.

Here is the updated command to lauch fileio example:

vsim -c -do fileio.do fileio

Modelsim: Generate vcd waveform

You can create vcd waveform using Modelsim and view it later using gtkwave.

This command specifies the name of the vcd file to dump the waveform into:

vcd file <vcd-filename>

Now that we have specified the vcd filename, we have to specify the signals which should be dumped into the vcd file. Lets find what signals are available in the project:

show -all

To add signal to vcd output:

vcd add <path_to_instance>/<signal-name>

You can now run the simulation and check in your working directory for the vcd file. You can open the vcd file using gtkwave.

To demonstrate, I will reuse the fileio example. These commands will create vcd file for fileio example:

vcd file fileio.vcd
vcd add *

To open the generated vcd file using gtkwave

gtkwave fileio.vcd

VHDL: File i/o as testbench stimulus

It is not always practical to hard code the test bench stimulus in VHDL code. This article introduces a way to read the stimulus stored in a text file and feed the DUT.

First, lets look at the DUT. It is a simple 4 bit adder.

Now lets create the test bench for gen.

The process input_gen reads the input from the input file “in.txt” and the process output_gen writes the output to output file “out.txt”.

The file variable inp_file opens the file “in.txt” in read mode and the file variable out_file opens the file “out.txt” in write mode. Both “in.txt” and “out.txt” are stored as text file.

Each line in “in.txt” has one stimulus for all signals as integers. In this example, we have only two signals i_a and i_b. This is the syntax of one line in “in.txt”:

{{i_a stimulus}} {{i_bstimulus}}

Here is an example “in.txt”:

One line is read from “in.txt” every clock cycle using readline function into inline variable. The stimulus for each variable are read serially from inline using read function.

Quartus: Launch test bench in modelsim

To use modelsim as the default simulator in quartus, please follow this blog post.

Step 1: Open settings dialog box by clicking Assignment->Settings menu or by using the keyboard shortcut Ctrl+Shift+E. The settings dialog box should appear.

Step 2: Select EDA Tool Settings->Simulation option in the sidebar.

Step 3: Enable test bench by selecting the option Compile test bench.

test_bench_enable

Step 4: Click Test Benches… button to create test benches. Test benches dialog should appear.

Step 5: Click New button to create new test bench. New Test Bench Settings dialog should appear.

test_bench_dialog

Step 6: In the New Test Bench Settings dialog, provide the name of your test bench using Test bench name.

Step 7: Add all the necessary test bench and implementation files by clicking File name ellipsis button.

new_tb_dialog

Step 8: Click Ok to create new test bench. Test Benches dialog should now list the test bench you created.

Step 9: Click Ok. Click Apply in Settings dialog box.

Step 10: To launch ModelSim simulator, you have to first Compile your design by clicking the Start compilation icon or by using the Ctrl+L shortcut.

Step 11: After the compilation is successfully completed, launch simulation by clicking RTL Simulation icon.

Quartus: set simulator for already existing project

In this post, I will show you how to change simulation tool for an existing project.

Changing simulation tool

Step 1: Open settings dialog box by clicking Assignment->Settings menu or by using the keyboard shortcut Ctrl+Shift+E. The settings dialog box should appear.

Step 2: Select EDA Tool Settings->Simulation option in the sidebar.

Simulation settings
Step 3: In the simulation settings page, select the required simulation tool using Tool name drop down box.

Setting simulation tool path

Now that you have instructed Quartus to use the simulation tool you wanted, you should also inform Quartus where it can find this tool.

Step 1: Open options dialog box by clicking Tools->Options menu. Options dialog box should open

Step 2: In the option dialog box, select General->EDA Tool options in the sidebar.

Step 3: in the EDA Tool options page, set the path to your desired tool.

EDA Tool options